UPD78P083 datasheet(39/58 Pages) RENESAS

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µPD78P083

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Data retention supply voltage

VDDDR

1.8

5.5

Data retention supply current

IDDDR

VDDDR = 1.8 V

0.1

µA

Release signal set time

tSREL

µs

Oscillation stabilization wait

tWAIT

Release by RESET

217/fx

time

Release by interrupt

Note

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85

°C)

Note 212/fxx or 214/fxx-217/fxx can be selected by bit 0-bit 2 (OSTS0-OSTS2) of oscillation stabilization time selection register

(OSTS).

Remark

fxx: Main system clock frequency (fx or fx/2)

fx: Main system clock oscillation frequency

Data Retention Timing (STOP mode released by RESET)

Data Retention Timing (Standby release signal: STOP mode released by interrupt signal)

STOP instruction execution

VDD

VDDDR

Operating

mode

HALT mode

STOP mode

Data retention mode

tWAIT

RESET

tSREL

Internal reset operation

STOP instruction execution

VDD

VDDDR

Standby release signal

(interrupt request)

Operating

mode

HALT mode

STOP mode

Data retention mode

tWAIT

tSREL

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