UPD78P083 datasheet(21/58 Pages) RENESAS

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µPD78P083

RESET

VPP

VDD

PGM

D0 to D7

Operating Mode

Page data latch

+12.5 V

+6.5 V

Data input

Page write

High-impedance

Byte write

Data input

Program verify

Data output

Program inhibit

High-impedance

Read

+5 V

Data output

Output disable

High-impedance

Standby

High-impedance

x : L or H

PROM PROGRAMMING

The

µPD78P083 has an internal 24-Kbyte PROM as a program memory. For programming, set the PROM programming

mode with the VPP and RESET pins. For the connection of unused pins, refer to “PIN CONFIGURATIONS (TOP VIEW)

(2) PROM programming mode.”

Caution

Programs must be written in addresses 0000H to 5FFFH (The last address 5FFFH must be specified).

They cannot be written by a PROM programmer which cannot specify the write address.

4.1

Operating Modes

When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming

mode is set. This mode will become the operating mode as shown in Table 4-1 when the CE, OE, and PGM pins are set

as shown.

Further, when the read mode is set, it is possible to read the contents of the PROM.

Table 4-1. Operating Modes of PROM Programming

UPD78P083 데이터시트(PDF) 21 Page - Renesas Technology Corp

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