M24128, M24C64, M24C32

DC and AC parameters

25/34

Table 17.

Test conditions specified in Table 11 and Table 8

Symbol

Alt.

Parameter

Min.

Max.

Unit

Clock Frequency

400

kHz

Clock Pulse Width High

600

ns

Clock Pulse Width Low

1300

ns

(1)

1.

Sampled only, not 100% tested.

SDA Fall Time

20

300

ns

100

ns

0

ns

Data Out Hold Time

200

ns

(2)

2.

To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the

falling or rising edge of SDA.

Clock Low to Next Data Valid (Access Time)

200

900

ns

(3)

3.

For a reSTART condition, or following a Write cycle.

600

ns

600

ns

600

ns

Time between Stop Condition and Next Start Condition

1300

ns

Write Time

5

ms

Table 18.

Test conditions specified in Table 11 and Table 9 or Table 10

Symbol

Alt.

Parameter

Min.

Max.

Unit

Clock Frequency

400

kHz

Clock Pulse Width High

600

ns

Clock Pulse Width Low

1300

ns

(1)

1.

Sampled only, not 100% tested.

SDA Fall Time

20

300

ns

100

ns

0

ns

Data Out Hold Time

200

ns

(2)

2.

To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the

falling or rising edge of SDA.

Clock Low to Next Data Valid (Access Time)

200

900

ns

(3)

3.

For a reSTART condition, or following a Write cycle.

600

ns

600

ns

600

ns

Time between Stop Condition and Next Start Condition

1300

ns

Write Time

10

ms