UPD17708 datasheet(320/358 Pages) RENESAS

320 / 358 page

318

µPD17704, 17705, 17707, 17708, 17709

21.4.4 Cautions on raising supply voltage VDD

The following points (1) and (2) must be noted when raising supply voltage VDD.

(1) To raise supply voltage VDD from level lower than power-ON clear voltage

Supply voltage VDD must be raised once to a level higher than 3.5 V.

Figure 21-8 illustrates this.

As shown in the figure, if a voltage less than 3.5 V is applied on application of VDD in a program that backs

up VDD at 2.2 V by using the clock stop instruction, the power-ON clear signal remains output, and the program

is not executed.

At this time, the output ports of the device output undefined values, increasing the current consumption in some

cases.

Consequently, the backup time when the device is backed up by batteries is substantially shortened.

Figure 21-8. Cautions on Raising VDD

VDD

BTM0CY flag

setting pulse

XOUT

5 V

3.5 V

2.2 V

0 V

Power-ON

clear signal

Power-ON

clear voltage

Operation stops

Halt status

50 ms

Because output ports are

undefined during this period,

current consumption may increase.

Power-ON reset

Progarm starts

Opera-

tion

stops

Normal operation

Back up

Initialize during this

period and then

execute clock stop

instruction

STOP s instruction

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