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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD17708 데이터시트(PDF) 152 Page - Renesas Technology Corp |
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UPD17708 데이터시트(HTML) 152 Page - Renesas Technology Corp |
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152 / 358 page  µPD17704, 17705, 17707, 17708, 17709 150 13.2 Basic Timer 0 13.2.1 Outline of basic timer 0 Figure 13-2 outlines basic timer 0. Basic timer 0 is used as a timer by detecting in software the BTM0CY flag that is set at fixed intervals (100, 50, 20, or 10 ms). If the BTM0CY flag is read first after power-ON reset, “0” is always read. After that, the flag is set to “1” at fixed intervals. If the CE pin goes high, CE reset is effected in synchronization with the timing at which the BTM0CY flag is set next. Therefore, a power failure can be detected by reading the content of the BTM0CY flag at system reset (power- ON reset or CE reset). For the details of power failure detection, refer to 21. RESET. Figure 13-2. Outline of Basic Timer 0 Remarks 1. BTM0CK1 and BTM0CK0 (bits 1 and 0 of basic timer 0 clock selection register: refer to Figure 13-3) set the time intervals at which the BTM0CY flag is set. 2. BTM0CY (bit 0 of basic timer 0 carry register: refer to Figure 13-4) detects the status of the flip-flop. Divider Clock selection block 4.5 MHz BTM0CY flag Selector BTM0CK0 flag BTM0CK1 flag Flip-flop |
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