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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD17708 데이터시트(PDF) 259 Page - Renesas Technology Corp |
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UPD17708 데이터시트(HTML) 259 Page - Renesas Technology Corp |
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259 / 358 page  257 µPD17704, 17705, 17707, 17708, 17709 Figure 17-3. Configuration of PLL Mode Selection Register 17.2.2 Outline of each division mode (1) Direct division mode (MF) In this mode, the VCOL pin is used. The VCOH pin is pulled down. In this mode, only the programmable counter is used for frequency division. (2) Pulse swallow mode (HF) In this mode, the VCOL pin is used. The VCOH pin is pulled down. In this mode, the swallow counter and programmable counter are used for frequency division. Name Flag symbol b3 P L L S C N F b2 0 b1 P L L M D 1 b0 P L L M D 0 Address 10H Read/Write R/W PLL mode selection Power-ON reset WDT&SP reset CE reset 1 Clock stop 0 1 0 1 0 0 0 0 Disables VCOL and VCOH pins Direct division (VCOL pin, MF mode) Pulse swallow (VCOH pin, VHF mode) Pulse swallow (VCOL pin, HF mode) Selects division mode of PLL frequency synthesizer U U R R U: Undefined R: Retained 0 0 0 1 1 Fixed to 0 0 0 0 0 Clears least significant bit to 0 Sets least significant bit to 1 Selects least significant bit of swallow counter 0 1 |
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