IP101G-DS-R01 datasheet(25/65 Pages) ETC

25 / 65 page

IP101G

Data Sheet

25/65

January 14, 2014

IP101G-DS-R01

Bit

Name

Description/Usage

Default value

(h):

0000

Received Code Word Bit 15

0, RO

Reserved

Acknowledge

Received Code Word Bit 14

0, RO

Message Page

Received Code Word Bit 13

0, RO

Acknowledge 2

Received Code Word Bit 12

0, RO

Toggle

Received Code Word Bit 11

0, RO

[10:0] Message/Unformatt

ed Field

Message/Unformatted Field

Received Code Word Bit 10:0

0, RO

The other Registers are reserved registers. User is inhibited to access to these registers. It may

introduce abnormal function to write these registers.

MII page16 register16

page

MII

ROM R/W

Description

Default

UTP PHY Specific Control Register

16[15:14]

RO Reserved

2’b00

16[13]

R/W RMII_V10

This bit combines with RMII_V12 bit for RMII mode settings.

16[12]

R/W RMII_V12

RMII_V10 RMII_V12 REPEATER

_MODE

(P16R16[2])

Mode

RMII back to back mode

RMII v1.2 CRS_DV will

toggle at the end

RMII v1.0 CRS_DV will not

toggle at the end

Note 1: “X” indicate don’t care (either 1 or 0).

Note 2: When RMII_v10 or RMII_v12 is selected, page16 reg16

bit2 should be also set to 1 to enable repeater mode. Then

CRS_DV will be asserted only when receive medium is nonidle.

16[11]

R/W AUTO_MDIX_DIS

Set high to disable the automatic switch of MDI and MDI-X

modes. For details, please refer to section 4 Auto-MDIX

function description.

16[10]

R/W Reserved

16[9]

R/W JABBER_ENABLE

Jabber function enable at 10Base-T

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