ES9826 datasheet(35/88 Pages) ESS

35 / 88 page

ES9826 Datasheet

VERSION 0.1.2

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM

PWM Signal

Output a configurable PWM signal. Frequency and duty cycle of PWM signal can be calculated with the following equations:

�� [��] =

��

��_�� + 1

�� [%] = (

��_��

��_�� + 1

) × 100

Configured with 8-bit value Register 33: PWM_COUNT and 16-bit value Registers 35-34: PWM_FREQ.

Analog Features

Programmable Gain Amplifier (PGA)

The ES9826 integrates an analog programmable gain amplifier (PGA) with a 0 to +30dB gain in increments of +3dB steps.

Applicable registers:

• Register 62: PGA GAIN CONTROL EN (defaults to 0)

• Register 67: ADC ATTEN SET

• Register 68: PGA GAIN CONTROL

• Register 72: PGA SETTINGS

Auto Ranging Enhancement (ARE)

The ES9826 introduces a new optional Auto Ranging Enhancement (ARE) function that broadens the dynamic range of the

source material while maintaining audio integrity.

ARE is available in software mode only. An ARE application note will be available from ESS FAE or distributor.

Clock Selection

The ES9826 requires a 49.152/45.1584MHz or 24.576/22.5792MHz clock. It can be provided from an external high quality

clock or it can be configured through the integrated PLL by setting the PLL dividers and enables.

• EN_MCLK_IN – Register 193[0]

Enables clock inputs to the digital core

• SEL_MCLK_IN – Register 193[2:1]

Selection of the ADC & digital core clock (ACLK/PLL)

• EN_PLL_CLK_IN – Register 193[3]

Enables SEL_PLL_IN source input

• SEL_PLL_CLK_IN – Register 193[5:4]

Selection of PLL clock source (ACLK or BCK)

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