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ES9826 데이터시트(PDF) 60 Page - ESS Technology,Inc |
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ES9826 데이터시트(HTML) 60 Page - ESS Technology,Inc |
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60 / 88 page ![]() ES9826 Datasheet VERSION 0.1.2 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM 60 ADC Registers Register 36: ADC DATAPATH CONTROL Bits [7] [6] [5] [4] [3] [2] [1] [0] Default 1'b1 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 Bits Mnemonic Description [7] RESERVED NA [6] BYPASS_FIR2X • 1'b0: Non-bypass (default) • 1'b1: Bypass DFir_2x [5] BYPASS_FIR4X • 1'b0: Non-bypass (default) • 1'b1: Bypass DFir_4x [4] BYPASS_IIR3 • 1'b0: Non-bypass (default) • 1'b1: Bypass IIR3 [3] BYPASS_IIR2 • 1'b0: Non-bypass (default) • 1'b1: Bypass IIR2 [2] BYPASS_IIR1 • 1'b0: Non-bypass (default) • 1'b1: Bypass IIR1 [1] CH1_AVG Sets the CH1 datapath input to an average of both analog inputs, (CH1 + CH2)/2. • 1'b0: Disabled (default) • 1'b1: Enabled [0] MONO_MODE Mute CH2 decimation path. • 1'b0: Disabled (default) • 1'b1: Enabled |
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