5CEBA2F13C6SC datasheet(24/37 Pages) INTEL

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PCIe Gen1 and Gen2 Hard IP

Cyclone V GX, GT, SX, and ST devices contain PCIe hard IP that is designed for

performance and ease-of-use. The PCIe hard IP consists of the MAC, data link, and

transaction layers.

The PCIe hard IP supports PCIe Gen2 and Gen1 end point and root port for up to x4

lane configuration. The PCIe Gen2 x4 support is PCIe-compatible.

The PCIe endpoint support includes multifunction support for up to eight functions, as

shown in the following figure. The integrated multifunction support reduces the FPGA

logic requirements by up to 20,000 LEs for PCIe designs that require multiple

peripherals.

Figure 9.

PCIe Multifunction for Cyclone V Devices

PCIe Link

External System

FPGA Device

Host CPU

Root

Complex

Local

Peripheral 1

Local

Peripheral 2

The Cyclone V PCIe hard IP operates independently from the core logic. This

independent operation allows the PCIe link to wake up and complete link training in

less than 100 ms while the Cyclone V device completes loading the programming file

for the rest of the device.

In addition, the PCIe hard IP in the Cyclone V device provides improved end-to-end

datapath protection using ECC.

External Memory Interface

This section provides an overview of the external memory interface in Cyclone V

devices.

Hard and Soft Memory Controllers

Cyclone V devices support up to two hard memory controllers for DDR3, DDR2, and

LPDDR2 SDRAM devices. Each controller supports 8 to 32 bit components of up to

4 gigabits (Gb) in density with two chip selects and optional ECC. For the Cyclone V

SoC devices, an additional hard memory controller in the HPS supports DDR3, DDR2,

and LPDDR2 SDRAM devices.

All Cyclone V devices support soft memory controllers for DDR3, DDR2, and LPDDR2

SDRAM devices for maximum flexibility.

Cyclone V Device Overview

683694 | 2018.05.07

Cyclone V Device Overview

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