Apart from lowering cost and power consumption, partial reconfiguration increases the

effective logic density of the device because placing device functions that do not

operate simultaneously is not necessary. Instead, you can store these functions in

external memory and load them whenever the functions are required. This capability

reduces the size of the device because it allows multiple applications on a single

device—saving the board space and reducing the power consumption.

Intel simplifies the time-intensive task of partial reconfiguration by building this

capability on top of the proven incremental compile and design flow in the Intel

Quartus Prime design software. With the Intel solution, you do not need to know all

the intricate device architecture details to perform a partial reconfiguration.

Partial reconfiguration is supported through the FPP x16 configuration interface. You

can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to

enable simultaneous partial reconfiguration of both the device core and transceivers.

Enhanced Configuration and Configuration via Protocol

Cyclone V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and

several configuration schemes.

Table 24.

Configuration Schemes and Features Supported by Cyclone V Devices

Mode

Data

Width

Max Clock

Rate

(MHz)

Max Data

Rate

(Mbps)

Decompressi

on

Design

Security

Partial

Reconfigurat

ion(18)

Remote

System

Update

AS through the EPCS

and EPCQ serial

configuration device

1 bit, 4

bits

100

—

Yes

Yes

—

Yes

PS through CPLD or

external

microcontroller

1 bit

125

125

Yes

Yes

—

—

FPP

8 bits

125

—

Yes

Yes

—

Parallel flash

loader

16 bits

125

—

Yes

Yes

Yes

CvP (PCIe)

x1, x2,

and x4

lanes

—

—

Yes

Yes

Yes

—

JTAG

1 bit

33

33

—

—

—

—

Instead of using an external flash or ROM, you can configure the Cyclone V devices

through PCIe using CvP. The CvP mode offers the fastest configuration rate and

flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone V CvP

implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

Related Information

Configuration via Protocol (CvP) Implementation in Intel FPGAs User Guide

Provides more information about CvP.

(18) The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with

the "SC" suffix in the part number. For device availability and ordering, contact your local Intel

sales representatives.

Cyclone V Device Overview

683694 | 2018.05.07

Cyclone V Device Overview

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