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WM8569SEDS/RV 데이터시트(PDF) 28 Page - Wolfson Microelectronics plc |
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WM8569SEDS/RV 데이터시트(HTML) 28 Page - Wolfson Microelectronics plc |
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28 / 36 page ![]() WM8569 Production Data w PD Rev 4.0 June 2006 28 ADC HIGHPASS FILTER DISABLE The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001100 ADC Control 3 ADCHPD 0 ADC Highpass Filter Disable: 0: Highpass filter enabled 1: Highpass filter disabled In left justified, right justified or I 2S modes, the ADCLRP register bit controls the polarity of ADCLRC. If this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown in Figure 13, Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the ADCLRP register bit is used to select between modes A and B. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION In Left/Right/I 2S Modes: ADCLRC Polarity (normal) 0: normal DACLRC polarity 1: inverted DACLRC polarity 0001100 Interface Control 4 ADCLRP 0 In DSP Mode: 0: DSP mode A 1: DSP mode B By default, ADCLRC and DOUT are sampled on the rising edge of ADCBCLK and should ideally change on the falling edge. Data sources that change ADCLRC and DOUT on the rising edge of ADCBCLK can be supported by setting the ADCBCP register bit. Setting ADCBCP to 1 inverts the polarity of ADCBCLK to the inverse of that shown in Figure 13 to Figure 19 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001100 Interface Control 5 ADCBCP 0 ADCBCLK Polarity (DSP Modes): 0: normal BCLK polarity 1: inverted BCLK polarity MUTE PIN DECODE The MUTE pin can either be used an output or an input. As an output it indicated 1024 consecutive zero samples to the DAC. By default selecting the MUTE to represent if the DAC has received more than 1024 midrail samples will cause the MUTE to be asserted as a softmute on the DAC. Disabling the decode block will cause any logical high on the MUTE pin to apply a softmute to the DAC. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001100 ADC Control 6 MPD 0 MUTE Pin Decode Disable: 0: MUTE pin decode enable 1: MUTE pin decode disable |
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