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WM8581 데이터시트(PDF) 32 Page - Wolfson Microelectronics plc

부품명 WM8581
상세설명  Multichannel CODEC with S/PDIF Transceiver
PDF  100 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8581 데이터시트(HTML) 32 Page - Wolfson Microelectronics plc

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WM8581
Production Data
w
PD Rev 4.0 April 2007
32
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
5
PAIFTXBCP
0
PAIF Receiver BCLK polarity
0 = BCLK not inverted
1 = BCLK inverted
1:0
SAIFFMT
[1:0]
10
SAIF Audio Data Format Select
11: DSP Format
10: I2S Format
01: Left justified
00: Right justified
3:2
SAIFWL
[1:0]
10
SAIF Audio Data Word Length
11: 32 bits (see Note 1,2)
10: 24 bits
01: 20 bits
00: 16 bits
4
SAIFLRP
0
In LJ/RJ/I
2S modes
0 = LRCLK not inverted
1 = LRCLK inverted
In DSP Format:
0 = DSP Mode A
1 = DSP Mode B
5
SAIFBCP
0
SAIF BCLK polarity
0 = BCLK not inverted
1 = BCLK inverted
R14
SAIF 2
0Eh
6
SAIF_EN
0
SAIF Enable
0 = SAIF disabled
1 = SAIF enabled
Table 16 Audio Interface Control
Notes
1.
Right Justified mode does not support 32-bit data. If word length xAIFxxWL=11b in Right
Justified mode, the word length is forced to 24 bits.
In all modes, the data is signed 2’s complement. The digital filters internal signal paths process
24-bit data. If the device is programmed to receive 16 or 20 bit data, the device pads the unused
LSBs with zeros. If the device is programmed into 32 bit mode, the 8 LSBs are ignored.
2.
In 24 bit I2S mode, any data width of 24 bits or less is supported provided that LRCLK is high for
a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles. If exactly 32 bit clocks
occur in one full left/right clock period the interface will auto detect and configure a 16 bit data
word length.



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