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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8593 데이터시트(PDF) 28 Page - Wolfson Microelectronics plc |
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WM8593 데이터시트(HTML) 28 Page - Wolfson Microelectronics plc |
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28 / 98 page  WM8593 Product Preview w PP Rev 1.0 January 2007 28 DIGITAL AUDIO INTERFACE CONTROL The control of the audio interface formats is achieved by register write. Dynamically changing the audio data format may cause erroneous operation and is not recommended. Interface timing is such that the input data and left/right clock are sampled on the rising edge of the interface bit clock. Output data changes on the falling edge of the interface bit clock. By setting the appropriate bit clock and left/right clock polarity bits, the WM8593 ADC and DACs can sample data on the opposite clock edges. The control of audio interface formats and clock polarities is summarised in Table 15. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1:0 DAC1_ FMT[1:0] 10 DAC1 Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I 2S 11 = DSP 3:2 DAC1_ WL[1:0] 10 DAC1 Audio Interface Word Length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in Right Justified mode) 4 DAC1_BCP 0 DAC1 BCLK Polarity 0 = DACBCLK not inverted - data latched on rising edge of BCLK 1 = DACBCLK inverted - data latched on falling edge of BCLK R2 DAC1_CTRL1 02h 5 DAC1_LRP 0 DAC1 LRCLK Polarity 0 = DACLRCLK not inverted 1 = DACLRCLK inverted 1:0 DAC2_ FMT[1:0] 10 DAC2 Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I 2S 11 = DSP 3:2 DAC2_ WL[1:0] 10 DAC2 Audio Interface Word Length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in Right Justified mode) 4 DAC2_BCP 0 DAC2 BCLK Polarity 0 = DACBCLK not inverted - data latched on rising edge of BCLK 1 = DACBCLK inverted - data latched on falling edge of BCLK R7 DAC2_CTRL1 07h 5 DAC2_LRP 0 DAC2 LRCLK Polarity 0 = DACLRCLK not inverted 1 = DACLRCLK inverted R13 ADC_CTRL1 0Dh 1:0 ADC_ FMT[1:0] 10 ADC Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I 2S 11 = DSP |
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