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WM8976 데이터시트(PDF) 85 Page - Wolfson Microelectronics plc |
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WM8976 데이터시트(HTML) 85 Page - Wolfson Microelectronics plc |
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85 / 108 page ![]() Pre-Production WM8976 w PP Rev 3.0 April 2006 85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0 ADCENL 0 Enable ADC: 0 = ADC disabled 1 = ADC enabled Analogue to Digital Converter (ADC) 8 OUT4EN 0 OUT4 enable 0 = disabled 1 = enabled Power Management 7 OUT3EN 0 OUT3 enable 0 = disabled 1 = enabled Power Management 6 LOUT2EN 0 LOUT2 enable 0 = disabled 1 = enabled Power Management 5 ROUT2EN 0 ROUT2 enable 0 = disabled 1 = enabled Power Management 3 RMIXEN 0 Right output channel mixer enable: 0 = disabled 1 = enabled Analogue Outputs 2 LMIXEN 0 Left output channel mixer enable: 0 = disabled 1 = enabled Analogue Outputs 1 DACENR 0 Right channel DAC enable 0 = DAC disabled 1 = DAC enabled Analogue Outputs 3 (03h) 0 DACENL 0 Left channel DAC enable 0 = DAC disabled 1 = DAC enabled Analogue Outputs 8 BCP 0 BCLK polarity 0=normal 1=inverted Digital Audio Interfaces 7 LRP 0 LRC clock polarity 0=normal 1=inverted Digital Audio Interfaces 6:5 WL 10 Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Digital Audio Interfaces 4:3 FMT 10 Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I 2S format 11= DSP/PCM mode Digital Audio Interfaces 2 DACLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=DAC data appear in ‘left’ phase of LRC 1=DAC data appears in ‘right’ phase of LRC Digital Audio Interfaces 4 (04h) 1 ADCLRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=ADC data appear in ‘left’ phase of LRC 1=ADC data appears in ‘right’ phase of LRC Digital Audio Interfaces |
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