전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

WM8976 데이터시트(PDF) 86 Page - Wolfson Microelectronics plc

부품명 WM8976
상세설명  Stereo CODEC With Speaker Driver
PDF  108 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8976 데이터시트(HTML) 86 Page - Wolfson Microelectronics plc

Back Button WM8976 Datasheet HTML 82Page - Wolfson Microelectronics plc WM8976 Datasheet HTML 83Page - Wolfson Microelectronics plc WM8976 Datasheet HTML 84Page - Wolfson Microelectronics plc WM8976 Datasheet HTML 85Page - Wolfson Microelectronics plc WM8976 Datasheet HTML 86Page - Wolfson Microelectronics plc WM8976 Datasheet HTML 87Page - Wolfson Microelectronics plc WM8976 Datasheet HTML 88Page - Wolfson Microelectronics plc WM8976 Datasheet HTML 89Page - Wolfson Microelectronics plc WM8976 Datasheet HTML 90Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 86 / 108 page
background image
WM8976
Pre-Production
w
PP Rev 3.0 April 2006
86
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
0
DACMONO
0
Selects between stereo and mono DAC operation:
0=Stereo device operation
1=Mono device operation. DAC data appears in
‘left’ phase of LRC
Digital Audio
Interfaces
8:6
000
Reserved
5
WL8
0
Companding Control 8-bit mode
0=off
1=device operates in 8-bit mode
Digital Audio
Interfaces
4:3
DAC_COMP
00
DAC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
Digital Audio
Interfaces
2:1
ADC_COMP
00
ADC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
Digital Audio
Interfaces
5 (05h)
0
LOOPBACK
0
Digital loopback function
0=No loopback
1=Loopback enabled, ADC data output is fed
directly into DAC data input.
Digital Audio
Interfaces
8
CLKSEL
1
Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
Digital Audio
Interfaces
7:5
MCLKDIV
010
Sets the scaling for either the MCLK or PLL clock
output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Digital Audio
Interfaces
4:2
BCLKDIV
000
Configures the BCLK output frequency, for use
when the chip is master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Digital Audio
Interfaces
1
0
Reserved
6 (06h)
0
MS
0
Sets the chip to be master over LRC and BCLK
0=BCLK and LRC clock are inputs
1=BCLK and LRC clock are outputs generated by
the WM8976 (MASTER)
Digital Audio
Interfaces



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com