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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8976 데이터시트(PDF) 26 Page - Wolfson Microelectronics plc |
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WM8976 데이터시트(HTML) 26 Page - Wolfson Microelectronics plc |
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26 / 108 page  WM8976 Pre-Production w PP Rev 3.0 April 2006 26 The polarity of the output signal can also be changed under software control using the ADCLPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 ADCLPOL 0 ADC polarity adjust: 0=normal 1=inverted R14 ADC Control 3 ADCOSR 0 ADC oversample rate select: 0=64x (lower power) 1=128x (best performance) Table 12 ADC Control SELECTABLE HIGH PASS FILTER A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 14. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 8 HPFEN 1 High Pass Filter Enable 0=disabled 1=enabled 7 HPFAPP 0 Select audio mode or application mode 0=Audio mode (1 st order, fc = ~3.7Hz) 1=Application mode (2 nd order, fc = HPFCUT) R14 ADC Control 6:4 HPFCUT 000 Application mode cut-off frequency See Table 14 for details. Table 13 ADC Enable Control SR=101/100 SR=011/010 SR=001/000 fs (kHz) HPFCUT [2:0] 8 11.025 12 16 22.05 24 32 44.1 48 000 82 113 122 82 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 156 131 180 156 131 180 156 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1). Values in Hz. Note that the High Pass filter values (when HPFAPP=1) are calculated with the assumption that the SR register bits are set correctly for the actual sample rate as shown in Table 14. |
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