AT89LP4052-20PI datasheet(42/90 Pages) ATMEL

42 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

Notes:

1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.

2. Enable the master SPI prior to the slave device.

3. Slave echoes master on the next Tx if not loaded with new data.

Table 18-1.

SPCR – SPI Control Register

SPCR Address = D5H

Reset Value = 0000 0000B

Not Bit Addressable

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

Bit

765432

Symbol

Function

SPIE

SPI interrupt enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES = 1

enable SPI interrupts. SPIE = 0 disables SPI interrupts.

SPE

SPI enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and P1.7.

SPI = 0 disables the SPI channel.

DORD

Data order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.

MSTR

Master/slave select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode.

CPOL

Clock polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not

transmitting. Please refer to figure on SPI clock phase and polarity control.

CPHA

Clock phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and

slave. Please refer to figure on SPI clock phase and polarity control.

SPR0

SPR1

SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no

effect on the slave. The relationship between SCK and the oscillator frequency, F

OSC., is as follows:

SPR1

SPR0

SCK

f/4

f/8

f/32

f/64

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