AT83SND1CXXX-ROTIL datasheet(143/212 Pages) ATMEL

143 / 212 page

143

4109J–8051–10/06

AT8xC51SND1C

Reset Value = 0000 0000b

Table 116. SBUF Register

SBUF (S:99h) – Serial Buffer Register

Reset value = XXXX XXXXb

Table 117. SADDR Register

Bit

Number

Bit

Mnemonic

Description

Framing Error Bit

To select this function, set SMOD0 bit in PCON register.

Set by hardware to indicate an invalid stop bit.

Must be cleared by software.

SM0

Serial Port Mode Bit 0

Refer to Table 113 for mode selection.

6SM1

Serial Port Mode Bit 1

Refer to Table 113 for mode selection.

5SM2

Serial Port Mode Bit 2

Set to enable the multiprocessor communication and automatic address

recognition features.

Clear to disable the multiprocessor communication and automatic address

recognition features.

4REN

Receiver Enable Bit

Set to enable reception.

Clear to disable reception.

3TB8

Transmit Bit 8

Modes 0 and 1: Not used.

Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.

2RB8

Receiver Bit 8

Mode 0: Not used.

Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit

received.

Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit

received.

1TI

Transmit Interrupt Flag

Set by the transmitter after the last data bit is transmitted.

Must be cleared by software.

0RI

Receive Interrupt Flag

Set by the receiver after the stop bit of a frame has been received.

Must be cleared by software.

7654

3210

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

Bit

Number

Bit

Mnemonic

Description

7 - 0

SD7:0

Serial Data Byte

Read the last data received by the serial I/O Port.

Write the data to be transmitted by the serial I/O Port.

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