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AT83SND1CXXX-ROTIL 데이터시트(PDF) 158 Page - ATMEL Corporation

부품명 AT83SND1CXXX-ROTIL
상세설명  Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
PDF  212 Pages
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제조업체  ATMEL [ATMEL Corporation]
홈페이지  http://www.atmel.com
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AT83SND1CXXX-ROTIL 데이터시트(HTML) 158 Page - ATMEL Corporation

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4109J–8051–10/06
AT8xC51SND1C
Figure 19-2. Complete Data Transfer on TWI Bus
The four operating modes are:
Master transmitter
Master receiver
Slave transmitter
•Slave receiver
Data transfer in each mode of operation are shown in Figure 19-3 through Figure 19-6. These
figures contain the following abbreviations:
A
Acknowledge bit (low level at SDA)
A
Not acknowledge bit (high level on SDA)
Data
8-bit data Byte
S
START condition
P
STOP condition
MR
Master Receive
MT
Master Transmit
SLA
Slave Address
GCA
General Call Address (00h)
R
Read bit (high level at SDA)
W
Write bit (low level at SDA)
In Figure 19-3 through Figure 19-6, circles are used to indicate when the serial interrupt flag is
set. The numbers in the circles show the status code held in SSSTA. At these points, a service
routine must be executed to continue or complete the serial transfer. These service routines are
not critical since the serial transfer is suspended until the serial interrupt flag is cleared by
software.
When the serial interrupt routine is entered, the status code in SSSTA is used to branch to the
appropriate service routine. For each status code, the required software action and details of the
following serial transfer are given in Table 126 through Table 19-6.
19.1.1
Bit Rate
The bit rate can be selected from seven predefined bit rates or from a programmable bit rate
generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 132). The
predefined bit rates are derived from the peripheral clock (F
PER) issued from the Clock Controller
block as detailed in section "Oscillator", page 12, while bit rate generator is based on timer 1
overflow output.
S
Slave Address
SCL
SDA
MSB
R/W
direction
ACK
signal
Nth data Byte
ACK
signal
P/S
bit
from
receiver
from
receiver
12
89
12
89
Clock Line Held Low While Serial Interrupts Are Serviced



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