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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT83SND1CXXX-ROTIL 데이터시트(PDF) 192 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL 데이터시트(HTML) 192 Page - ATMEL Corporation |
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192 / 212 page  192 4109J–8051–10/06 AT8xC51SND1C 22.4.0.5 Timings Test conditions: capacitive load on all pins= 50 pF. Table 159. SPI Interface Master AC Timing V DD = 2.7 to 3.3 V, TA = -40 to +85°C Note: 1. Value of this parameter depends on software. Symbol Parameter Min Max Unit Slave Mode T CHCH Clock Period 2 T PER T CHCX Clock High Time 0.8 T PER T CLCX Clock Low Time 0.8 T PER T SLCH, TSLCL SS Low to Clock edge 100 ns T IVCL, TIVCH Input Data Valid to Clock Edge 40 ns T CLIX, TCHIX Input Data Hold after Clock Edge 40 ns T CLOV, TCHOV Output Data Valid after Clock Edge 40 ns T CLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns T CLSH, TCHSH SS High after Clock Edge 0 ns T SLOV SS Low to Output Data Valid 50 ns T SHOX Output Data Hold after SS High 50 ns T SHSL SS High to SS Low (1) T ILIH Input Rise Time 2 μs T IHIL Input Fall Time 2 μs T OLOH Output Rise time 100 ns T OHOL Output Fall Time 100 ns Master Mode T CHCH Clock Period 2 T PER T CHCX Clock High Time 0.8 T PER T CLCX Clock Low Time 0.8 T PER T IVCL, TIVCH Input Data Valid to Clock Edge 20 ns T CLIX, TCHIX Input Data Hold after Clock Edge 20 ns T CLOV, TCHOV Output Data Valid after Clock Edge 40 ns TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TILIH Input Data Rise Time 2 μs TIHIL Input Data Fall Time 2 μs TOLOH Output Data Rise time 50 ns TOHOL Output Data Fall Time 50 ns |
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