AT89C51CC02CA-RATUM datasheet(94/156 Pages) ATMEL

94 / 156 page

AT/T89C51CC02

4126J–CAN–05/06

Registers

Table 56. CANGCON Register

CANGCON (S:ABh)

CAN General Control Register

Reset Value = 0000 0000b

ABRQ

OVRQ

TTC

SYNCTTC

AUTOBAUD

TEST

ENA

GRES

Bit Number

Bit Mnemonic

Description

ABRQ

Abort Request

Not an auto-resetable bit. A reset of the ENCH bit (message object

control & DLC register) is done for each message object. The

pending transmission communications are immediately aborted but

the on-going communication will be terminated normally, setting

the appropriate status flags, TxOk or RxOk.

6OVRQ

Overload Frame Request (Initiator).

Auto-resetable bit.

Set to send an overload frame after the next received message.

Cleared by the hardware at the beginning of transmission of the

overload frame.

5TTC

Network in Timer Trigger Communication

set to select node in TTC.

clear to disable TTC features.

SYNCTTC

Synchronization of TTC

When this bit is set the TTC timer is caught on the last bit of the

End Of Frame.

When this bit is clear the TTC timer is caught on the Start Of

Frame.

This bit is only used in the TTC mode.

3AUTOBAUD

AUTOBAUD

set to active listening mode.

Clear to disable listening mode

2TEST

Test mode. The test mode is intended for factory testing and not for

customer use.

1ENA/STB

Enable/Standby CAN Controller

When this bit is set, it enables the CAN controller and its input

clock.

When this bit is clear, the on-going communication is terminated

normally and the CAN controller state of the machine is frozen (the

ENCH bit of each message object does not change).

In the standby mode, the transmitter constantly provides a

recessive level; the receiver is not activated and the input clock is

stopped in the CAN controller. During the disable mode, the

registers and the mailbox remain accessible.

Note that two clock periods are needed to start the CAN controller

state of the machine.

0GRES

General Reset (Software Reset).

Auto-resetable bit. This reset command is ‘ORed’ with the

hardware reset in order to reset the controller. After a reset, the

controller is disabled.

AT89C51CC02CA-RATUM 데이터시트(PDF) 94 Page - ATMEL Corporation

AT89C51CC02CA-RATUM 데이터시트(HTML) 94 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL