AT89C51CC02CA-RATUM datasheet(41/156 Pages) ATMEL

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AT/T89C51CC02

4126J–CAN–05/06

Figure 17. Reading Procedure

Note:

aa = 10 for the Hardware Security Byte.

Flash Protection from Parallel

Programming

The three lock bits in Hardware Security Byte (See ’In-System Programming’ section)

are programmed according to Table 24 provide different level of protection for the on-

chip code and data located in FM0 and FM1.

The only way to write this bits are the parallel mode. They are set by default to level 3.

Table 24. Program Lock bit

Note:

1. Program Lock bits

U: unprogrammed

P: programmed

WARNING: Security level 2, 3 and 4 should only be programmed after Flash and Core

verification.

Preventing Flash Corruption

See Section “Power Management”.

Flash Spaces Reading

Flash Spaces Mapping

FCON = 00000aa0b

Data Read

DPTR = Address

ACC= 0

Exec: MOVC A, @A+DPTR

Clear Mode

FCON = 00h

Program Lock bits

Protection Description

Security

Level

LB0

LB1

LB2

No program lock features enabled.

Parallel programming of the Flash is disabled.

Same as 2, also verify through parallel programming interface is

disabled. This is the factory defaul programming.

UUP

Same as 3

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