T89C51AC2-SLSIM datasheet(24/121 Pages) ATMEL

24 / 121 page

A/T89C51AC2

4127G–8051–05/06

Internal Space

Lower 128 Bytes RAM

The lower 128 Bytes of RAM (see Figure 11) are accessible from address 00h to 7Fh

using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4

banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 18)

select which bank is in use according to Table 16. This allows more efficient use of code

space, since register instructions are shorter than instructions that use direct address-

ing, and can be used for context switching in interrupt service routines.

Table 16. Register Bank Selection

The next 16 Bytes above the register banks form a block of bit-addressable memory

space. The C51 instruction set includes a wide selection of single-bit instructions, and

the 128 bits in this area can be directly addressed by these instructions. The bit

addresses in this area are 00h to 7Fh.

Figure 12. Lower 128 Bytes Internal RAM Organization

Upper 128 Bytes RAM

The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

Expanded RAM

The on-chip 1024 Bytes of expanded RAM (XRAM) are accessible from address 0000h

to 03FFh using indirect addressing mode through MOVX instructions. In this address

range, the bit EXTRAM in AUXR register is used to select the XRAM (default) or the

XRAM. As shown in Figure 11 when EXTRAM = 0, the XRAM is selected and when

EXTRAM = 1, the XRAM is selected.

The size of XRAM can be configured by XRS1-0 bit in AUXR register (default size is

1024 Bytes).

Note:

Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and

must then be initialized properly.

RS1

RS0

Description

Bit-Addressable Space

4 Banks of

8 Registers

R0-R7

30h

7Fh

(Bit Addresses 0-7Fh)

20h

2Fh

18h

1Fh

10h

17h

08h

0Fh

00h

07h

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