BL702/704/706 Datasheet

2.10.11 QDEC

The chip has built-in three sets of quadrature decoders, which are used to decode the two sets of pulses with a phase

difference of 90 degrees generated by the dual-channel rotary encoder into the corresponding speed and rotation.

Direction.

QDEC clock source can be 32K (f32k_clk) or 32M (xclk), with 16-bit pulse count range (-32768~32767 pulse/sample),

with 12 configurable sample periods (32us~131ms per sample at 1MHz) ), with a 16-bit settable report period (0~65535

ample/report).

2.10.12 ADC

The chip has a built-in 12bits successive approximation analog-to-digital converter (ADC) with a maximum working

clock of 2MHz, supports 12 external analog inputs and several internal analog signal selections, and supports single-

channel conversion and multi-channel scanning modes.

ADC can work in two modes of single conversion and multi-channel scanning. It supports 2.0V, 3.2V optional internal

reference voltage, and the conversion result is 12/14/16bits (achieved by oversampling) left-justified mode.

The ADC has a FIFO with a depth of 32, supports a variety of interrupts, and supports DMA operations.

In addition to measuring common analog signals, ADC can also be used to measure power supply voltage. In addition,

ADC can also be used for temperature detection by measuring internal/external diode voltage.

2.10.13 DAC

The chip has a built-in 10bits digital-to-analog converter (DAC) with a FIFO depth of 1 word and supports 2 DAC

modulation outputs. Can be used for audio playback, conventional analog signal modulation, DAC input clock can be

selected as 32M or Audio PLL, support DMA to transfer memory to the DAC modulation register, DAC output pin is

fixed to ChannelA to GPIO11, ChannelB to GPIO17.

2.10.14 Debug interface

Support standard JTAG 4-wire debugging interface, and use debuggers such as Jlink/OpenOCD/CK Link for debug-

ging.

BL702/704/706 Datasheet

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