DSP56F803 datasheet(27/57 Pages) FREESCALE

27 / 57 page

56F803 Technical Data, Rev. 16

Freescale Semiconductor

Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-14)

3.3 AC Electrical Characteristics

Timing waveforms in Section 3.3 are tested using the V

IL and VIH levels specified in the DC Characteristics

table. In Figure 3-2 the levels of V

IH and VIL for an input signal are shown.

This low-voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential

as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed

under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is

generated).

This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is

regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not

be generated unless the external power supply drops below the minimum specified value (3.0V).

10. Power

–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is

ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate

is. The internally regulated voltage is typically 100mV less than VDD during ramp-up, until 2.5V is reached, at which time it

self-regulates.

120

180

Freq. (MHz)

150

IDD Digital

IDD Analog

IDD Total

DSP56F803 데이터시트(PDF) 27 Page - Freescale Semiconductor, Inc