TMS320F datasheet(49/389 Pages) TI

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Multiplication Section

4-5

Central Processing Unit

4.2

Multiplication Section

The ’C24x uses a 16-bit

× 16-bit hardware multiplier that can produce a signed

or unsigned 32-bit product in a single machine cycle. As shown in Figure 4–5,

the multiplication section consists of:

- The 16-bit temporary register (TREG), which holds one of the multipli-

cands

- The multiplier, which multiplies the TREG value by a second value from

data memory or program memory

- The 32-bit product register (PREG), which receives the result of the multi-

plication

- The product shifter, which scales the PREG value before passing it to the

CALU

Figure 4–5. Block Diagram of the Multiplication Section

MUX

PREG

Multiplier

×16

TREG

Product shifter (32 bits)

Multiplication

section

From data memory

From data

memory

From program memory

To CALU

From data memory

To data memory

To high word

of PREG

4.2.1

Multiplier

The 16-bit

× 16-bit hardware multiplier can produce a signed or unsigned

32-bit product in a single machine cycle. The two numbers being multiplied are

treated as 2s-complement numbers, except during unsigned multiplication

(MPYU instruction). Descriptions of the inputs to, and output of, the multiplier

follow.

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