USB97C102 datasheet(48/80 Pages) SMSC

부품명	USB97C102

상세설명	Multi-Endpoint USB Peripheral Controller with Integrated 5 Port HUB

PDF	80 Pages

Scroll/Zoom	100%

제조업체	SMSC [SMSC Corporation]

홈페이지	http://www.smsc.com

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48 / 80 page

SMSC DS – USB97C102

Page 48

Rev. 03/23/2000

Table 87 - Receive Packet Number FIFO Register

RXFIFO

(0x7F58)

NEXT RX PACKET NUMBER FIFO REGISTER

BIT

NAME

R/W

DESCRIPTION

RXFIFO_EMPTY

1 = No pending packets from the host to be processed

RXFIFO_FULL

1 = The SIEDMA will not accept packets from the host (via RX

Overflow)

Reserved

[4:0]

P[4:0]

Packet Number

When a packet has been received, and the 8-byte header has

been written by the SIEDMA, the associated Packet Number is

placed in this FIFO.

A "complete" reception requires that the 8 byte status header is correctly written into the packet buffer, with the

correct data, and moved into the RX Packet Number FIFO. A "successful" reception requires that the CRC and PID

check bits of a

"complete" reception are good. The hardware queues only "complete" packets. Firmware must

determine if "complete" packets were "successful". Corrupted token packets causes the complete data payload to be

ignored.

USB97C102 데이터시트(PDF) 48 Page - SMSC Corporation