TMS320DM647 datasheet(5/166 Pages) TI

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Contents

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

TMS320DM647/TMS320DM648 Digital Media

Peripheral Information and Electrical

Processor

.................................................. 1

Specifications

........................................... 56

1.1

Features

.............................................. 1

6.1

Parameter Information

.............................. 56

6.2

Recommended Clock and Control Signal Transition

1.1.1

Trademarks

.......................................... 2

Behavior

............................................. 58

1.2

Description

............................................ 2

6.3

Power Supplies

...................................... 58

1.3

Functional Block Diagram

............................ 4

6.4

PLL1 and PLL1 Controller

........................... 63

Device Overview

......................................... 6

6.5

PLL2 and PLL2 Controller

........................... 67

2.1

Device Characteristics

................................ 6

6.6

Enhanced Direct Memory Access (EDMA3)

2.2

CPU (DSP Core) Description

......................... 7

Controller

............................................ 70

2.3

C64x+ CPU

.......................................... 10

6.7

Reset Controller

..................................... 83

2.4

Memory Map Summary

............................. 12

6.8

Interrupts

............................................ 90

2.5

Pin Assignments

.................................... 15

6.9

DDR2 Memory Controller

........................... 94

2.6

Terminal Functions

.................................. 19

6.10

External Memory Interface A (EMIFA)

.............. 96

2.7

Device Support

...................................... 33

6.11

Video Port

.......................................... 104

2.8

Device and Development-Support Tool

6.12

VCXO Interpolated Control (VIC)

.................. 112

Nomenclature

....................................... 35

6.13

Universal Asynchronous Receiver/Transmitter

2.9

Documentation Support

............................. 36

(UART)

............................................. 114

Device Configuration

.................................. 38

6.14

Inter-Integrated Circuit (I2C)

....................... 116

3.1

System Module Registers

........................... 38

6.15

Host-Port Interface (HPI) Peripheral

............... 120

3.2

Bootmode Registers

................................ 38

6.16

Peripheral Component Interconnect (PCI)

......... 131

3.3

Debugging Considerations

.......................... 47

6.17

Multichannel Audio Serial Port (McASP)

3.4

Pullup/Pulldown Resistors

........................... 47

Peripheral

.......................................... 136

System Interconnect

................................... 49

6.18

3-Port Ethernet Switch Subsystem (3PSW)

....... 144

4.1

Internal Buses, Bridges, and Switch Fabrics

........ 49

6.19

Management Data Input/Output (MDIO)

........... 153

4.2

Data Switch Fabric Connections

.................... 49

6.20

Timers

.............................................. 155

4.3

Configuration Switch Fabric

......................... 51

6.21

VLYNQ Peripheral

................................. 157

Device Operating Conditions

........................ 53

6.22

General-Purpose Input/Output (GPIO)

............. 160

5.1

Absolute Maximum Ratings Over Operating

6.23

IEEE 1149.1 JTAG

................................. 163

Temperature Range (Unless Otherwise Noted)

..... 53

Mechanical Data

....................................... 165

5.2

Recommended Operating Conditions

............... 54

7.1

Thermal Data for ZUT

.............................. 165

5.3

Electrical Characteristics Over Recommended

7.1.1

Packaging Information

............................. 165

Ranges of Supply Voltage and Operating

Temperature (Unless Otherwise Noted)

............ 55

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