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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMS320DM647 데이터시트(PDF) 98 Page - Texas Instruments |
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TMS320DM647 데이터시트(HTML) 98 Page - Texas Instruments |
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98 / 166 page  www.ti.com 6.10.3 EMIFA Electrical Data/Timing AECLKIN 2 3 4 4 5 1 TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 Table 6-29. Timing Requirements for AECLKIN for EMIFA (1) (2) (see Figure 6-13) -720 -900 NO. UNIT MIN MAX 1 tc(EKI) Cycle time, AECLKIN 6(3) 40 ns 2 tw(EKIH) Pulse duration, AECLKIN high 2.7 ns 3 tw(EKIL) Pulse duration, AECLKIN low 2.7 ns 4 tt(EKI) Transition time, AECLKIN 2 ns 5 tJ(EKI) Period Jitter, AECLKIN 0.02E(4) ns (1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. (2) E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA. (3) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. (4) This timing applies only when AECLKIN is used for EMIFA. Figure 6-13. AECLKIN Timing for EMIFA Peripheral Information and Electrical Specifications 98 Submit Documentation Feedback |
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