PCF8531USLASH2 datasheet(7/44 Pages) PHILIPS

7 / 44 page

2000 Feb 11

Philips Semiconductors

Product speciﬁcation

× 128 pixel matrix driver

PCF8531

FUNCTIONAL DESCRIPTION

8.1

Oscillator

The on-chip oscillator provides the clock signal for the

display system. No external components are required and

the OSC input must be connected to VDD. An external

clock signal, if used, is connected to this input.

8.2

Power-on reset

The on-chip Power-on reset initializes the chip after

Power-on or power failure.

8.3

I2C-bus controller

The I2C-bus controller receives and executes the

commands. The PCF8531 acts as an I2C-bus slave

receiver and therefore cannot control bus communication.

8.4

Input ﬁlters

To enhance noise immunity in electrically adverse

environments, RC low-pass filters are provided on the

SDA and SCL lines.

8.5

Display data RAM

The PCF8531 contains a 34

× 128 bits static RAM, which

stores the display data. The RAM is divided into 6 banks of

128 bytes (6

× 8 × 128 bits). Bank 6 is used for icon data.

During RAM access, data is transferred to the RAM via the

I2C-bus interface. There is a direct correspondence

between the X address and column output number.

8.6

Timing generator

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the data buses.

8.7

Address counter

The address counter sets the addresses of the display

data RAM for writing.

8.8

Display address counter

The display address counter generates the addresses for

read out of the display data.

8.9

Command decoder

The command decoder identifies command words that

arrive on the I2C-bus and determines the destination for

the following data bytes.

8.10

Bias voltage generator

The bias voltage generator generates four buffered

intermediate bias voltages. This block contains the

generator for the reference voltages and the four buffers.

This block can operate in two voltage ranges:

• Normal mode; 4.0 to 9.0 V

• Power save mode; 3.0 to 9.0 V.

8.11

VLCD generator

The VLCD voltage generator contains a configurable

2 to 5 times voltage multiplier; this is software

programmable.

8.12

Reset

The PCF8531 has the possibility of two reset modes,

internal Power-on reset or external reset (RES). The reset

mode is selected using the ENR signal. After a reset, the

chip has the following state:

• All row and column outputs are set to VSS (display off)

• RAM data is undefined

• Power-down mode.

8.13

Power-down

During power-down, all static currents are switched off (no

internal oscillator, no timing and no LCD segment drive

system), and all LCD outputs are internally connected to

VSS. The I2C-bus function remains operational.

8.14

Column driver outputs

The LCD drive section includes 128 column outputs

(C0 to C127) which should be connected directly to the

LCD. The column output signals are generated in

accordance with the multiplexed row signals and with the

data in the display latch. When less than 128 columns are

required, the unused column outputs should be left open

circuit.

8.15

Row driver outputs

The LCD drive section includes 34 row outputs

(R0 to R33), which should be connected directly to the

LCD. The row output signals are generated in accordance

with the selected LCD drive mode. If less than 34 rows or

lower Mux rates are required, the unused outputs must be

left open circuit. The row signals are interlaced i.e. the

selection order is R0, R2, ..., R1, R3 etc.

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