TMD3721 datasheet(59/89 Pages) OSRAM

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Page 58

Datasheet, Public

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[v3-00] 2023-May-26

TMD3721 − Register O ver view

ASD_L Register (Address 0xE0)

Figure 80:

ASD_L Register

ASD_H Register (Address 0xE1)

Figure 81:

ASD_H Register

The ASD (ALS Start Delay) timing registers control the start of

ALS integration after detect of VSYNC signal. It is a 16-bit value

split into two registers {ASD_H [7:0], ASD_L [7:0]}.

ASD is recommended to be programmed greater than ALS

initialization period (24 cycles), otherwise it is ignored. ASD

needs to be programmed less than VSYNC period, since the

counter will reset once VSYNC signal is detected. If VSYNC is

changed, ASD period and other configurations need to be

changed accordingly by bringing device in IDLE mode by

stopping integration.

Addr: 0xE0

ASD_L

Bit

Bit Name

Default

Access

Bit Description

7:0

ASD_L

0x00

ASD_L is lower byte of ASD (ALS Start Delay).

Value

Delay Cycles

Delay Time

0x0000

ALS init time

0x0018

ALS init time

0x0019

1.357μs x 25

0x001A

1.357μs x 26

……

…

0xFFFF

65535

1.357μs x 65535

Addr: 0xE1

ASD_H

Bit

Bit Name

Default

Access

Bit Description

7:0

ASD_H

0x00

ASD_H is upper byte of ASD (ALS Start Delay).

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