TMD3721 datasheet(62/89 Pages) OSRAM

62 / 89 page

Datasheet, Public

Page 61

[v3-00] 2023-May-26

Document Feedback

TMD3721 − Register Overview

Although ASP1, ASP2, ATIME are programmed with high

flexibility, it always recommend to program ATIME to be an

integer multiple of ASP1+ASP2. Explained by a formula:

ATIME =N x(ASP1 +ASP2), where N is a positive integer.

ATIME Register (Address 0xE6)

Figure 86:

ATIME Register

The ATIME register controls the integration time of the ALS

ADCs. The timer is implemented with a down counter with 0x00

as the terminal count. The timer is clocked at a 2.779ms nominal

rate. Loading 0x00 will generate a 2.779ms integration time,

loading 0x01 will generate a 5.558ms integration time, and so

forth.

By default, ALS data are sampled and stored in FIFO registers

by every ATIME period. If enable ASP1 ASP2, ALS data sampling

period is defined by ASP1 ASP2.

Addr: 0xE6

ATIME

Bit

Bit Name

Default

Access

Bit Description

7:0

ATIME

0x00

The ATIME value specifies the ALS integration time in

2.779ms intervals. 0x00 indicates 2.779ms. The maximum ALS

count value depends on the integration time. For every

2.779ms, the maximum value increases by 2048. This means

that to be able to reach ALS full scale, the integration time has

to be at least 32*2.779ms.

Value

Integration

Cycles

Integration

Time

Maximum

ALS Value

0x00

2.779ms

2047

0x01

5.558ms

4095

0x02

8.336

6143

……

…

0x1F

88.923ms

65535

……

…

0xFF

256

711.381ms

65535

TMD3721 데이터시트(PDF) 62 Page - OSRAM GmbH

TMD3721 데이터시트(HTML) 62 Page - OSRAM GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

데이터시트 다운로드

링크 URL