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AD9516-0/PCBZ 데이터시트(PDF) 72 Page - Analog Devices

부품명 AD9516-0/PCBZ
상세설명  14-Output Clock Generator with Integrated 2.8 GHz VCO
PDF  84 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9516-0/PCBZ 데이터시트(HTML) 72 Page - Analog Devices

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AD9516-0
Rev. 0 | Page 72 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
F4
<1:0> OUT4
LVPECL power-down modes.
Power-Down <1> <0>
Mode
Output
0
0
Normal operation.
On
0
1
Partial power-down, reference on; use only if there are no external load resistors.
Off
1
0
Partial power-down, reference on, safe LVPECL power-down.
Off
1
1
Total power-down, reference off; use only if there are no external load resistors.
Off
F5
<4>
OUT5 Invert
Sets the output polarity.
<4> = 0; noninverting.
<4> = 1; inverting.
F5
<3:2> OUT5 LVPECL Sets the LVPECL output differential voltage (VOD).
Differential
<3> <2> VOD (mV)
Voltage
0
0
400
0
1
600
1
0
780
1
1
960
F5
<1:0> OUT5
LVPECL power-down modes.
Power-Down <1>
<0> Mode
Output
0
0
Normal operation.
On
0
1
Partial power-down, reference on; use only if there are no external load resistors.
Off
1
0
Partial power-down, reference on, safe LVPECL power-down.
Off
1
1
Total power-down, reference off; use only if there are no external load resistors.
Off
Table 56. LVDS/CMOS Outputs
Reg.
Addr
(Hex) Bit(s) Name
Description
140
<7:5> OUT6 Output Polarity
In CMOS mode, <7:5> select the output polarity of each CMOS output.
In LVDS mode, only <5> determines LVDS polarity.
<7> <6>
<5> OUT6A (CMOS)
OUT6B (CMOS)
OUT6 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
140
<4>
OUT6 CMOS B
In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.
<4> = 0; turn off the CMOS B output.
<4> = 1; turn on the CMOS B output.
140
<3>
OUT6 Select LVDS/CMOS
Select LVDS or CMOS logic levels.
<3> = 0; LVDS.
<3> = 1; CMOS.
140
<2:1> OUT6 LVDS Output Current
Set output current level in LVDS mode. This has no effect in CMOS mode.
<2>
<1> Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100
1
0
5.25
50
1
1
7
50



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