AD9516-0SLASHPCBZ datasheet(78/84 Pages) AD

78 / 84 page

AD9516-0

Rev. 0 | Page 78 of 84

Table 60. System

Reg.

Addr

(Hex) Bit(s) Name

Description

230

<2>

Power-Down Sync

Power down the SYNC function.

<2> = 0; normal operation of the SYNC function.

<2> = 1; power-down sync circuitry.

230

<1>

Power-Down Distribution Reference

Power down the reference for distribution section.

<1> = 0; normal operation of the reference for the distribution section.

<1> = 1; power down the reference for the distribution section.

230

<0>

Soft SYNC

The soft SYNC bit works the same as the SYNC pin, except that the polarity of this bit

reversed. That is, a high level forces selected channels into a predetermined static

state, and a 1-to-0 transition triggers a sync.

<0> = 0; same as SYNC high.

<0> = 1; same as SYNC low.

Table 61. Update All Registers

Reg.

Addr

(Hex) Bit(s) Name

Description

232

<0>

Update All

Registers

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens

on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.

<0> = 1 (self-clearing); update all active registers to the contents of the buffer registers.

AD9516-0/PCBZ 데이터시트(PDF) 78 Page - Analog Devices