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LR4102 데이터시트(PDF) 18 Page - LSI Computer Systems |
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LR4102 데이터시트(HTML) 18 Page - LSI Computer Systems |
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18 / 32 page ![]() 18 TinyRISC LR4102 Microprocessor Figure 5 Input Timing with Respect to PBCLKP Figure 6 Output Timing with Respect to PBCLKP Figure 7 Input Timing with Respect to SDCLKP Setup Input PBCLKP Hold Note: PBCLKP equals the system clock (PCLKP) when the DIV C value in the Clock module is 0b01. DIV C = 0b01 is used to show timing for signals related to the system clock. The setting of DIV C only affects PBCLKP and the timing for signals related to the FAPI clock (PBCLKP). Min Output Output PBCLKP Max Output Setup Input SDCLKP Hold |
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