LR4102 datasheet(16/32 Pages) LSI

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TinyRISC LR4102 Microprocessor

FBus Interface

TRDYN

Target ready

Bidirectional

Test Interface

CSHTSTP

Cache test enable

Input

IDDTN

IDD test

Input

JTAGALSOP

JTAG controller present

Input

PMON_OUTP

Process monitor output

Output

SCAN_ENABLEP

Enable scan chain loading

Input

SCAN__INP

Input to the scan chain

Input

SCAN_MODEP

Enable scan testing

Input

SCAN_OUTP

Output from the scan chain

Output

SCAN_RAMWEP

RAM write enable

Input

SELECT_CKOUT1N

Select PLL test

Input

3-state all LR4102 output and bidirectional

signals

Input

Power Lines

VDD, VDD2

VDD for CPU core and oscillator 2.5 V or

1.8 V

Power

VDD4

VDD for I/O 3.3 V

Power

PLLVDD1

VDD to PLL 2.5 V. Requires VDD CPU core

and oscillator at 2.5 V, since PLL must be

disabled for VDD CPU core and clock at

1.8 V

Power

VSS, VSS2, VSS4,

PLLVSS1

VSS for CPU core, clock, I/O and PLL

Power

Table 5

LR4102 Signal List (Cont.)

Signal Group

Mnemonic Name

Functional Description

I/O

(Sheet 4 of 4)

LR4102 데이터시트(PDF) 16 Page - LSI Computer Systems

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