LR4102 datasheet(13/32 Pages) LSI

13 / 32 page

TinyRISC LR4102 Microprocessor

Signal Descriptions

The signals are described in alphabetical order by mnemonic. Each

signal deﬁnition contains the mnemonic and the full signal name.

Mnemonics for signals that are active LOW end in an “N”, and

mnemonics for signals that are active HIGH end in a “P.” In the

descriptions that follow, the verb

assert means to drive active. The verb

deassert means to drive inactive.

The LR4102 signals are divided into the following groups:

• Control Signals

• Clocking Interface

• Timer Interface

• SerialICE-1 Interface

• EJTAG Interface and JTAG boundary scan signals

• PC Trace Output

• FBus Interface

• Test Interface

• Power Lines

Table 5 lists all of the LR4102 signals, grouped by interface.

Table 5

LR4102 Signal List

Signal Group

Mnemonic Name

Functional Description

I/O

Control Signals

RESETN

Asynchronous system reset

Input

BIG_ENDIANP

Big/Little Endian select

Input

CWAITIP

Wait for interrupt (low power mode)

Output

INTP[5:0]

Condition/Interrupt

Input

DEBUGMP

Debug mode

Output

(Sheet 1 of 4)

LR4102 데이터시트(PDF) 13 Page - LSI Computer Systems

LR4102 데이터시트(HTML) 13 Page - LSI Computer Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

데이터시트 다운로드

링크 URL