SAF7113 datasheet(44/80 Pages) PHILIPS

44 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

Fig.30 Vertical timing diagram for 60 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR

or fast mode (HTC = 01 or 11)].

HREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7H.

ODD: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = AH.

VS: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to 00 and/or RTSE13 to RTSE10 = BH.

V123: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = CH.

VREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = EH.

FID: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = FH.

(1) Line numbers in parenthesis refer to ITU line counting.

(2) VREF range short or long can be programmed via I2C-bus bit VRLN.

The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.

The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.

(3) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP, see Table 52.

(4) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the

field is even. If HREF is inactive during the falling edge of V123, the field is odd. The specific position of the slope is dependent on the internal

processing delay and may change a few clock cycles from version to version.

handbook, full pagewidth

RTS0/1 VS

VRLN = 1(2)

(b) 2nd field

(a) 1st field

input CVBS

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(20)

(3)

(2)

(1)

(525)

(21)

(22)(1)

VRLN = 1(3) (2)

VRLN = 0(3) (2)

525

524

523

522

(266)

(267)

(268)

(269)

(270)

(271)

(272)

(273)

(274)

(283)

(284)

(265)

(264)

(263)

(262)

263

264

265

266

267

268

269

270

271

280

281

262

261

260

259

(285)(1)

282

MHB337

520

× 2/LLC

RTS0/1 ODD

× 2/LLC

VRLN = 0(2)

RST0/1 HREF

RTS0/1 VREF

RTS0/1 VS

RTS0/1 HREF

input CVBS

RTS0/1 ODD

RTS0/1 V123(4)

RTS0/1 FID(3)

RTS0/1 V123(4)

RTS0/1 FID(3)

SAF7113 데이터시트(PDF) 44 Page - NXP Semiconductors

SAF7113 데이터시트(HTML) 44 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

데이터시트 다운로드

링크 URL