SC2000 datasheet(8/44 Pages) PHILIPS

8 / 44 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC2000

Microprocessor Interface Registers

The four 8-bit Microprocessor Interface

Registers comprise the command and

control port for the SC2000.

Command/Status Register

Busy (CS_0): This bit is automatically

set to 1 when a command that requires

synchronization with the SC2000’s in-

ternal state machine has been initiated.

The bit is cleared to 0 when the com-

mand has been completed. The follow-

ing commands require synchronization:

• Destination Routing Memory Write

• Source Routing Memory Write

• Parallel Access Destination Write

• Parallel Access Source Read

Read (CS_1): Setting this bit to 1 ini-

tiates a read of the register pointed to

by the contents of the Internal Address

cleared to 0 the contents of the selected

and High Byte Data Registers. Once the

READ operation is complete the READ

bit is cleared automatically.

Write (CS_2): Setting this bit to 1 ini-

tiates a write to the register pointed to

by the contents of the Internal Address

cleared to 0 the contents of the Low Byte

and High Byte Data Registers have been

transferred into the selected register.

Once the WRITE operation is com-

pleted the WRITE bit is cleared auto-

matically.

Terminate (CS_3):

Setting this bit to 1

terminates any command that requires

synchronization with the SC2000’s in-

ternal state machine. This command is

needed to complete a command when

the SC2000’s internal state machine has

stopped running due to the failure of the

system clocks. The command currently

being executed is completed asynchro-

nously and the BUSY bit is cleared to 0.

To restore normal operation the TER-

MINATE bit must be explicitly cleared

to 0. This bit can be read back for verifi-

cation purposes.

Command/Status Register

BIT

R/W

Command/Status

CS_0: Busy (S)

CS_1: Read (C)

CS_2: Write (C)

R/W

CS_3: Terminates (C)

CS_4: Reserved

CS_5: Reserved

CS_6: Reserved

R/W

CS_7: Reset (C)

Note:

(1) Bit 0 is the LSB of the byte.

(2) Initiating multiple commands in a

single access is not recommended.

CPU Interface Register Map

A_1

A_0

Command/Status

Internal Address

Low Byte Data

High Byte Data

Low Byte Data Register

BIT

R/W

Function

R/W

D_0

R/W

D_1

R/W

D_2

R/W

D_3

R/W

D_4

R/W

D_5

R/W

D_6

R/W

D_7

Note:

Bit 0 is the LSB of the byte.

High Byte Data Register

BIT

R/W

Function

R/W

D_8

R/W

D_9

R/W

D_10

R/W

D_11

R/W

D_12

R/W

D_13

R/W

D_14

R/W

D_15

Note:

Bit 0 is the LSB of the byte.

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