STR910FAM32X6 datasheet(59/78 Pages) STMICROELECTRONICS

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STR91xFA

Electrical characteristics

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Critical Data corruption (control registers...)

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened to

prevent unrecoverable errors occurring (see application note AN1015).

6.12.7 Electrical Sensitivities

Notes:

Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC

specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

6.13

External memory bus timings

VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C, CL= 30 pF unless otherwise specified.

Table 24.

EMI Bus Clock Period

Notes: 1 The internal EMI Bus clock signal is available externally only on LFBGA144 packages (ball M8),

and not available on LQFP packages.

2 EMI_ratio =1/ 2 by default (can be programmed to be 1 by setting the proper bits in the

SCU_CLKCNTR register)

Table 25.

EMI read operation

Symbol

Parameter

Conditions

Class 1)

Static latch-up class

TA=+25°C

DLU

Dynamic latch-up class

VDDQ=3.3V, VDD=1.8V,

fOSC/fCPUCLK=4 MHz/96 MHz

Symbol

Parameter

Value

tBCLK

EMI Bus Clock period

1 /(fHCLK x EMI_ratio)

Symbol

Parameter

Value

Unit

Min

Max

tRCR

Read to CSn inactive

-1

tRP

Read Pulse Width

(WSTRD-WSTOEN+1) x

tBCLK - 1

(WSTRD-WSTOEN+1) x

tBCLK + 1

tRDS

Read Data Setup Time

tRDH

Read Data Hold Time

tRAS

Read Address Setup Time

(WSTOEN) x tBCLK- 1

(WSTOEN) x tBCLK + 1

tRAH

Read Address Hold Time

tAW

ALE pulse width

(ALE_LENGTH) x tBCLK - 1

(ALE_LENGTH) x tBCLK + 1

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