SZF2002 datasheet(64/76 Pages) PHILIPS

64 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

2. The operating supply current is measured with all output pins disconnected; CLK driven with tr =tf =10ns;

VIL =VSS;VIH =VDD; EA = RST = Port 0 = VDD.

3. The Idle mode supply current is measured with all output pins disconnected; CLK driven with tr =tf = 10 ns; VIL =VSS;

VIH =VDD; EA = Port 0 = VDD.

4. The power-down current is measured with all output pins disconnected; CLK connected to VSS; EA = Port 0 = VDD;

RST=VSS.

5. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage

below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1.

26 ADC CHARACTERISTICS

Notes

1. All ADC inputs require an external divide-by-2 voltage divider.

2. Gain error: the maximum difference between actual and ideal slope.

3. Zero-offset error: the difference between the actual and ideal input voltage corresponding to the first actual code

transition.

4. Differential non-linearity: the difference between the actual and ideal code widths.

5. Integral non-linearity: maximum deviation from straight line.

6. Channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken

from different channels under the same temperature, voltage and frequency conditions. Not tested, but verified on

sampling basis.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

VIN(ADC)

ADC input voltage

note 1

VSSA

−

0.5VDDA

VDDA

analog supply voltage

VDD − 0.5

−

VDD + 0.5

IDDA

supply current operating

VDDA = 3.0 V; fclk = 8 MHz

−−

0.5

CAIN

analog on-chip input capacitance

−−

2pF

RAIN

analog on-chip input impedance

−−

Ω

Gain error; note 2

−1

−

OSe

zero-offset error; note 3

−1

−

LSB

DNL

differential non-linearity; note 4

−0.5

−

+0.5

LSB

INL

Integral non-linearity; note 5

−1

−

LSB

Mctc

channel-to-channel matching;

note 6

−−

±1⁄2

LSB

VI(slope)

input voltage slope

fclk = 8 MHz

−0.15

−

+0.15

V/ms

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