SZF2002 datasheet(29/76 Pages) PHILIPS

29 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

16 I2C-BUS SERIAL I/O

The serial port supports the twin line I2C-bus, which

consists of a data line (SDA) and a clock line (SCL). These

lines also function as the I/O port lines P1.7 and P1.6

respectively.

The system is unique because data transport, clock

generation, address recognition and bus control arbitration

are all controlled by hardware.

The I2C-bus serial I/O has complete autonomy in byte

handling and operates in 4 modes:

• Master transmitter

• Master receiver

• Slave transmitter

• Slave receiver.

These functions are controlled by the Serial Control

contents may also be used as a vector to various service

routines. S1DAT is the Data Shift Register and S1ADR is

the Slave Address Register. Slave address recognition is

performed by on-chip hardware.

Figure 15 shows the block diagram of the I2C-bus

serial I/O.

Fig.15 Block diagram of I2C-bus serial I/O.

MLB199

SLAVE ADDRESS

S1ADR

SHIFT REGISTER

S1DAT

SDA

ARBITRATION

SYNC LOGIC

SCL

BUS CLOCK GENERATOR

S1STA

S1CON

CONTROL REGISTER

STATUS REGISTER

SZF2002 데이터시트(PDF) 29 Page - NXP Semiconductors

SZF2002 데이터시트(HTML) 29 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

데이터시트 다운로드

링크 URL