AM79C940KCSLASHW datasheet(24/144 Pages) AMD

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Am79C940

CLSN

Collision (Input/Output)

An external indication that a collision condition has

been detected by the (internal or external) Medium

Attachment Unit (MAU), and that signals from two or

more nodes are present on the network. When the AUI

port is selected (PORTSEL [1–0] = 00), CLSN will be

activated when the CI

± input pair is receiving a collision

indication from the external transceiver. CLSN will be

asserted high for the entire duration of the collision

detection, but will not be asserted during the SQE Test

message following a transmit message on the AUI.

When the 10BASE-T port is selected (PORTSEL [1–0]

= 01), CLSN will be asserted high when simultaneous

transmit and receive activity is detected (logically

detected when TXD

±/TXP± and RXD± are both active).

When the DAI port is selected (PORTSEL [1–0] = 10),

CLSN will be asserted high when simultaneous trans-

mit and receive activity is detected (logically detected

when RXCRS and TXEN are both active). When the

GPSI port is selected (PORTSEL [1–0] = 11), an input

from the external Manchester encoder/decoder signal-

ing the MACE device that a collision condition has

been detected on the network, and any receive frame

in progress should be aborted.

External Address Detection Interface

(EADI)

SF/BD

Start Frame/Byte Delimiter (Output)

The external indication that a start of frame delimiter

has been received. The serial bit stream will follow on

the Serial Receive Data pin (SRD), commencing with

the destination address field. SF/BD will go high for 4

bit times (400 ns) after detecting the second 1 in the

SFD of a received frame. SF/BD will subsequently

toggle every 400 ns (1.25 MHz frequency) with the

rising edge indicating the start (first bit) in each

subsequent byte of the received serial bit stream.

SF/BD will be inactive during frame transmission.

SRD

Serial Receive Data (Output)

SRD is the decoded NRZ data from the network. It is

available for external address detection. Note that

when the 10BASE-T port is selected, transition on SRD

will only occur during receive activity. When the AUI or

DAI port is selected, transition on SRD will occur

dur ing both transmit and receive activity.

CLSN Configuration

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

EAM/R

External Address Match/Reject(Input)

The incoming frame will be received dependent on the

receive operational mode of the MACE device, and the

polarity of the EAM/R pin. The EAM/R pin function is

programmed by use of the M/R bit in the Receive

Frame Control register. If the bit is set, the pin is config-

ured as EAM. If the bit is reset, the pin is configured as

EAR. EAM/R can be asserted during packet reception

to accept or reject packets based on an external

address comparison.

SRDCLK

Serial Receive Data Clock (Input/Output)

The Serial Receive Data (SRD) output is synchronous

to SRDCLK running at the 10MHz receive data clock

frequency. The pin is configured as an input, only when

the GPSI port is selected. Note that when the

10BASE–T port is selected, transition on SRDCLK will

only occur during receive activity. When the AUI or DAI

port is selected, transition on SRDCLK will occur during

both transmit and receive activity.

SLEEP

PORTSEL

[1-0]

ENDPLSIO

Interface Description

Pin Function

Sleep Mode

High Impedance

AUI

CLSN Output

10BASE-T

CLSN Output

1101

DAI Port

CLSN Output

GPSI

CLSN Output

Status Disabled

High Impedance (Note 2)

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