AM79C940KCSLASHW datasheet(78/144 Pages) AMD

78 / 144 page

Programmer’s Register Model (continued)

Addr

Mnemonic

Contents

R/W

FIFOCC

FIFO Configuration Control

XMTFW

Transmit FIFO Watermark (2 bits)

Assert TDTREQ after 8 write cycles can be made

Assert TDTREQ after 16 write cycles can be made

Assert TDTREQ after 32 write cycles can be made

RCVFW

Receive FIFO Watermark (2 bits)

Assert RDTREQ after 16 bytes are present

Assert RDTREQ after 32 bytes are present

Assert RDTREQ after 64 bytes are present

XMTFWU

Transmit FIFO Watermark Update–loads XMTFW bits

RCVFWU

Receive FIFO Watermark Update–loads

RCVFW bits

XMBRST

Select Transmit Burst mode

RCVBRST

Select Receive Burst mode

R/W

MACCC

Media Access Control (MAC) Configuration Control

PROM

Promiscuous mode

DXMT2PD

Disable Transmit Two Part Deferral

EMBA

Enable Modified Back-off Algorithm

–

DRCVPA

Disable Receive Physical Address

DRCVBC

Disable Receive Broadcast

ENXMT

Enable Transmit

ENRCV

Enable Receive

R/W

PLSCC

Physical Layer Signalling (PLS) Configuration Control

XMTSEL

Transmit Mode Select: 1➔ DO

± =1 during IDLE

PORTSEL [1:0]–Port Select (2 bits)

AUI selected

10BASE-T selected

DAI port selected

GPSI selected

ENPLSIO

Enable Status

R/W

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