AM79C940KCSLASHW datasheet(76/144 Pages) AMD

76 / 144 page

Programmer’s Register Model

Addr Mnemonic

Contents

R/W

RCVFIFO

Receive FIFO–16 bits

XMTFIFO

Transmit FIFO–16 bits

XMTFC

Transmit Frame Control

DRTRY

Disable Retry

DXMTFC

Disable Transmit FCS

APADXMT

Auto Pad Transmit

R/W

XMTFS

Transmit Frame Status

XMTSV

Transmit Status Valid

UFLO

Underflow

LCOL

Late Collision

MORE than one retry was needed

ONE

Exactly ONE retry occurred

DEFER

Transmission was deferred

LCAR

Loss of Carrier

RTRY

Transmit aborted after 16 attempts

R/W

XMTRC

EXDEF

Excessive Defer

–

XMTRC [3:0]

4-bit Transmit Retry Count

RCVFC

Receive Frame Control

LLRCV

Low Latency Receive

M/R

Match/Reject for external address detection

ASTRPRCV

Auto Strip Receive–Strips pad and FCS from

received frames

R/W

RCVFS

Receive Frame Status–4 bytes–read in 4 read cycles

RFS0

RCVCNT [7:0] Receive Message Byte Count

RFS1

RCVSTS, RCVCNT [11:8]–Receive Status & Receive Msg Byte Count MSBs

OFLO

Receive FIFO Overflow

CLSN

Collision during reception

FRAM

Framing Error

FCS

FCS (CRC) error

RCVCNT [11:8] 4 MSBs of Receive Msg. Byte Count

RFS2

RNTPC [7:0]

Runt Packet Count (since last successful reception)

RFS3

RCVCC [7:0]

Receive Collision Count (since last successful

reception)

FIFOFC

FIFO Frame Count

RCVFC

Receive Frame Count–# of RCV frames in FIFO

XMTFC

Transmit Frame Count–# of XMT frames in FIFO

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