| 전자부품 데이터시트 검색엔진 |
|
SCF5249VM140 데이터시트(PDF) 37 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
SCF5249VM140 데이터시트(HTML) 37 Page - Freescale Semiconductor, Inc |
|
37 / 56 page ![]() Electrical Characteristics SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 37 Figure 9. SDRAM Write Cycle Table 23. Debug AC Timing Specification Num Characteristic Units Min Max D1 PSTCLK to signal Valid (Output valid) --- 6 nSec D2 PSTCLK to signal Invalid (Output hold) 1.8 — nSec D31 Signal Valid to PSTCLK (Input setup) 3 — nSec D4 PSTCLK to signal Invalid (Input hold) 5 — nSec 1. DSCLK and DSI are internally synchronized. This setup time must be met only if recognition on a particular clock is required. 2. AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is different, the input and output timing specifications would need to be adjusted to match the clock load. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |