SCF5249VM140 datasheet(19/56 Pages) FREESCALE

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Signal Descriptions

SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

Freescale Semiconductor

8.7

Bus Buffer Signals

As the SCF5249 has a quite complicated slave bus, with the possibility to put DRAM on the bus, put

asynchronous memories on the bus, and to put ISA bus peripherals on the bus, it may become necessary

to introduce a bus buffer on the bus. The SCF5249 has a glueless interface to steer these bus buffers with

2 bus buffer output signals BUFENB1/GPIO57 and BUFENB2/GPIO7.

NOTE

The BUFENB2 signal is only used in the 160 MAPBGA package.

8.8

I2C Module Signals

There are two I2C interfaces on this device.

The I2C module acts as a quick two-wire, bidirectional serial interface between the SCF5249 processor

and peripherals with an I2C interface (e.g., LED controller, A-to-D converter, D-to-A converter). When

devices connected to the I2C bus drive the bus, they will either drive logic-0 or high-impedance. This can

be accomplished with an open-drain output.

8.9

Serial Module Signals

The following signals transfer serial data between the two UART modules and external peripherals.

All serial module signals can be used as gpi or gpo. The GPIO-FUNCTION and GPIO1-FUNCTION

registers must be programmed to determine pin functions of the inputs and outputs. If used as gpo or gpi,

UART functionality is lost.

Table 6. I2C Module Signals

I2c Module Signal

Description

I2C Serial Clock

The SCL/QPSICLK and SCL2/GPIO3 bidirectional signals are

the clock signal for first and second I2C module operation. The

I2C module controls this signal when the bus is in master

mode; all I2C devices drive this signal to synchronize I2C

timing.

Signals are multiplexed

Function select is done via PLLCR register.

I2C Serial Data

The SDA/QSPI_DIN and SDA2/GPIO55 bidirectional signals

are the data input/output for the first and second serial I2C

interface.

Signals are multiplexed

Function select is done via PLLCR register.

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