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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7LITE49M 데이터시트(PDF) 67 Page - STMicroelectronics |
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ST7LITE49M 데이터시트(HTML) 67 Page - STMicroelectronics |
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67 / 188 page  ST7LITE49M Power saving modes 67/188 Figure 33. AWUFH mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 17: Interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. RESET INTERRUPT 3) Y N N Y CPU MAIN OSC PERIPHERALS 2) I[1:0] BITS OFF OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU MAIN OSC PERIPHERALS I[1:0] BITS ON OFF XX 4) ON CPU MAIN OSC PERIPHERALS I[1:0] BITS ON ON XX 4) ON 256 CPU CLOCK DELAY WATCHDOG ENABLE DISABLE WDGHALT 1) 0 WATCHDOG RESET 1 CYCLE AWU RC OSC ON AWU RC OSC OFF AWU RC OSC OFF HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) |
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