ST7LITE49M datasheet(125/188 Pages) STMICROELECTRONICS

125 / 188 page

ST7LITE49M

On-chip peripherals

125/188

Note:

If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the

Master to re-synchronize communication, get the transmission acknowledged and the bus

released for further communication

Bit 0 = GCAL General Call bit (slave mode).

This bit is set by hardware when a general call address is detected on the bus while

ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the

interface is disabled (PE=0).

0: No general call address detected on bus

1: general call address detected on bus

I2C Clock Control register (CCR)

Reset value: 0000 0000 (00h)

Bit 7 = FM/SM Fast/Standard I2C mode bit

This bit is set and cleared by software. It is not cleared when the interface is disabled

(PE=0).

0: Standard I2C mode

1: Fast I2C mode

Bit 6:0 = CC[6:0] 7-bit clock divider bits

These bits select the speed of the bus (FSCL) depending on the I

2C mode. They are not

cleared when the interface is disabled (PE=0).

Refer to the Electrical Characteristics section for the table of values.

Note:

The programmed FSCL assumes no load on SCL and SDA lines.

I2C Data register (DR)

Reset Value: 0000 0000 (00h)

Bit 7:0 = D[7:0] 8-bit Data register

These bits contain the byte to be received or transmitted on the bus.

–

Transmitter mode: byte transmission start automatically when the software writes

in the DR register.

–

Receiver mode: the first data byte is received automatically in the DR register

using the least significant bit of the address. Then, the following data bytes are

received one by one after reading the DR register.

FM/SM

CC6

CC5

CC4

CC3

CC2

CC1

CC0

Read / Write

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